(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of forming void free inter-metal dielectrics with improved gap filling and thermal characteristics.
(2) Description of the Related Art
Inter-metal dielectrics are insulative materials that are used for insulating metal interconnect layers in semiconductor devices, as is well known in the art. As the dimensions of the metal lines are shrinking ever so fast in order to realize increased device content and higher switching speeds on integrated circuits, the spacings between the lines are also decreasing to less than 0.2 micrometers. Consequently, it is getting more and more difficult to fill the gaps between the lines with the conventional insulative dielectrics such as doped silicate glasses including borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorosilicate glass (FSG).
A typical example of the type of problem encountered with poor filling of a gap is shown in FIG. 1a. Here, in the cross-section of a semiconductor substrate, two conducting lines (20) are formed on substrate (10). Insulative dielectric layer (30) is formed over the substrate including gap (G) between the lines. It is found in the present manufacturing line that with gaps approaching 0.2 xcexcm, air gaps, voids, and key-holes (40), as they are sometimes referred to in the art, are formed in between the lines, as shown in FIG. 1a. Although air gaps may aid in reducing the effective dielectric constant of the insulative layer, and hence that of the capacitive coupling between the lines to improve speed, generally they are more harmful than being helpful as they can cause reliability problems such as delaminations, shorts, and so on, as is well known in the art.
Furthermore, with closer spacings of deep submicron technologies, the aspect ratio of the height to gap spacing becomes high, sometimes more than 2, thereby making that much more difficult the filling of the gap in between the lines. It will be appreciated by those skilled in the art that the problem of high aspect ration is exacerbated even further in the presence of oxide spacersxe2x80x94reference numeral (50) in FIG. 1bxe2x80x94that are often used in the manufacture of integrated circuit chips.
A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is disclosed by Lee, et al., in U.S. Pat. No. 6,033,981. A substrate is provided with narrowly spaced conductive lines. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and the substrate. The HDP layer is etched through to expose the edges of the conducting lines. An insulating layer is deposited overlying the HDP layer and conducting lines. A chemical mechanical polishing (CMP) is used to remove the peaks of the insulating layer, exposing the HDP layer in the area overlying the conducting lines. The exposed HDP layer is etched away exposing the top surface of the conducting lines. The insulating layer is then selectively etched away. Spacers are then added along the sidewalls of the conductor. Finally, a second HDP layer is deposited overlying the first dielectric layer and conducting lines free from voids.
In another U.S. Pat. No. 6,140,221, Annapragada, et al., teach a method of forming vias through a porous insulative dielectric layer of a semiconductor device. In this method, a first via is formed in the porous dielectric layer, which in turn is filled with a less porous dielectric material. Then a second via is formed through the less porous material. The vias so formed are said to be useful for porous insulative layers that include aero gel materials.
In still another method for filling narrow gaps shown in U.S. Pat. No. 6,096,654, Kirchoff, et al., use a doped silicate glass having a dopant concentration in a bottom portion thereof which is grater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.
The present invention teaches a different, two-step gap filling process for forming inter-metal dielectric layer without void formation, but with improved gap filling, and additionally, with improved thermal characteristics, as described in the embodiments of the invention.
It is therefore an object of the present invention to provide a method of forming inter metal dielectric (IMD) layers in high aspect ratio gaps between metal lines without the attendant problems of having voids, key-holes.
It is another object of the present invention to provide a two-step filling process for forming IMD layers.
It is an overall object of the present invention to provide a void free IMD integration process with improved gap filling and improved thermal characteristics for a more reliable semiconductor device.
These objects are accomplished by providing a substrate; forming a metal line pattern over said substrate; forming a liner layer over said metal line pattern including over a gap between two adjacent metal lines; forming a first insulative layer conformally covering said liner layer; forming a photoresist layer over said substrate and then partial stripping said photoresist layer only to leave a portion of said photoresist in said gap so as to reduce the aspect ratio of said gap between said metal lines; removing said first insulative layer partially only to leave that portion underlying and surrounding said portion of said photoresist layer in said gap between said metal lines; removing said portion of said photoresist layer remaining in said gap; filling said gap of said reduced aspect ratio with a second insulative layer so as to avoid the problem of forming voids in otherwise deep, high aspect ratio gaps; and forming an oxide layer over said second insulative layer on said substrate, and chemical mechanical polishing said oxide layer.